Our High-Speed Wireline Building Block -- A 112 Gbps PAM-4 T/2-Spaced 5-Tap FFE in 0.13-um BiCMOS -- is presented at ICTA 2019 by first-year graduate student Kanan Wang.  The acceptance rate of this year is about 50%, and the submissions are quite competitive. ICTA 2019 is held in Chengdu this year and will be moved to Nanjing in 2020.

Congratulations to Kanan. 

For more detials, please visit http://www.ieee-icta.cn/.

Abstract—A 5-tap T/2-spaced 112-Gb/s Feed-Forward Equalizer (FFE) with four-level pulse-amplitude modulation (PAM-4) in a 0.13-m BiCMOS process is presented. A number of bandwidth enhancement techniques are used, which allow high-speed operation while consuming 113.2 mW from a 1.8-V supply. The gain ripple of each delay tap is less than 1 dB up to 28 GHz to ensure low jitter. In addition, a 3-tap T-spaced 112-Gb/s PAM-4 FFE is designed and compared with this work to showcase the pronounced advantage of T/2-spaced FFE in PAM-4 equalization.