(1.)Basic Information

Chenyang Ge
Professor
3D Perception、CV、Robot、AI
VLSI、SoC

(7.)Contact

 

 

SoC Design Center
Xi’an Jiaotong University
28 Xianning West Street, Xi’an, 710049 CHINA
+86-29-82668672 cyge@mail.xjtu.edu.cn
http://cyge.gr.xjtu.edu.cn

 

(6.)Teaching

Academic Discipline:
1) Pattern Recognition and Intelligent system(National Key Academic Discipline)
2) Microelectronic and Solid State Electronic (National Key Academic Discipline)

DTV Group:
The group is composed by young teachers,  masters and Ph.D, has set up since 1994.

Main Responsibility

  1. National Technology Invention Award of China, the Second Prize. Nanning Zheng, Chenyang Ge, Hongbin Sun, Jianru Xue, Jizhong Zhao, Dong Wang. 2007.
  2. Ministry of Education of China for New Century Excellence Talent, 2010.
  3. Province Young Science and Technology Award of Shannxi, the Eighth Session. Chenyang Ge. 2010.

(3.)Education

Sep.2005-Dec.2009.   Xi’an Jiaotong University Xi’an, China.  Ph. D., Control Science and Engineering
Sep.1999-July.2002.   Xi’an Jiaotong University Xi’an, China  M.S., Pattern Recognition and Intelligence System
Sep.1995-July.1999.   Xi’an Jiaotong University Xi’an, China  B.S., Electrical Engineering 
Jun.2006-Sep.2006.    IMEC Research Center Leuven, Belgium, Micro-electronic Training

(5.)Scientific Research

1.Digital TV Chip (3DTV)
Digital TV Chips are used in all kinds of digital TV, such as CRT, LCD, PDP and OLED, are used to connect between flat display component and various signal sources. The main functional blocks include AFE, analog video decoder (2D/3D adaptive comb filter), de-interlacing, frame rate up conversion, 3D adaptive denoise, adaptive motion compensation desawtooth, film pattern detection, scaler, smart image improvement, graphics OSD and MCU. The chip can reduce large screen flicker and cross-color, improve the quality and subjective definition of TV.
                                  

2.High-definition 3D Display Processing Chip for HMD
The chip has the ability to display 3D images for the CVBS, YPbPr or VGA stereo signals, supporting 1080P. It can be used in 3DTV, Head Mounted Display (HMD), micro-projector and so on. It is implemented by a pipeline architecture and includes the functional blocks such as PAL/NTSC decoder (2D/3D adaptive comb filter), 150Msps/ 10bits AFE, 120Hz format converter, video scaling double-engine, smart image improvement, 3D display controller and on-screen display (OSD).
                                        

3.LED Display Control Technology and Its Embedded Application
LED display control technology is used to control the large screen LED color display panels. And also, we use it to control the back-light of LED-TV, can reduce the TV energy cost adaptively with the different picture. We design an embedded LED product (LED Lantern). It can display the color image and text dynamically with the connection between modern lighting technology and China traditional culture.
                                     
                                                                                                           CES 2011

4.Stereo Vision Chip

Team Members

  1. National Science and Technology Important Specific Projects of China. “Development and Industrialization of Digital TV SoC Chip”. Principal Investigator. Jan.2009-Dec.2012.
  2. National Development and Reform Commission Industrial Projects of China. “Research and Development of Digital HDTV Video Processing Chip”. Principal Investigator. Mar. 2007-Oct.2009.
  3. National High Technology Research and Development Program of China (863 Virtual Reality). “Research and Development of Wide Field View of Head Mounted Display”. Principal Investigator. Jan.2009-Dec.2010.
  4. National High Technology Research and Development Program of China (863 VLSI). “Research and Development of Heterogeneous Multi-core Media Processor”. Principal Investigator. May.2005-Oct.2007.
  5. National High Technology Research and Development Program of China (863 VLSI). “Development of Video Scan Format Conversion Chip”. Principal Investigator. March.2003-May.2005.
  6. Ministry of Education for New Century Excellence Talent Supporting Program. Principal Investigator. Jan.2011-Dec.2013.
  7. Changhong Company Research Project. “Video Scaler IP Core”. Principal Investigator. June.2007 -May.2008.

(2.)Positions

  1. Chenyang Ge, Nanning Zheng. “VLSI Design on 3D Display Processing Chip for Binocular Stereo Displays”. High Technology Letters. 16(3): 288-230, 2010.
  2. Chenyang Ge, Nanning Zheng, Kuizhi Mei, Jizhong Zhao. “VLSI Design on 3D Display Processing Chip for Head-Mounted Display”. IEEE Consumer Electronics Society’s Games Innovation Conference 2009 (ICE-GIC 09).
  3. Chenyang Ge, Nanning Zheng, Pengju Ren, Yao Feng. “Design and Implement of Flat Panel TV Digital Video Post-process Chip”. Journal of Xi’an Jiaotong University. 42(10): 1285-1289, Oct.2008.
  4. Chenyang Ge, Nanning Zheng, Pengju Ren. "VLSI Design of Image Scaling IP Core Based on Mixed Interpolation Algorithm". Journal of Xi'an Electronic and Technology University. 37(1): 158-162, 2010.
  5. Chenyang Ge, Chao Zhang. "Research and Develop of Flat Panel TV Image Improving IP Core". Electronic Device. 31(5): 1413-1416, 2008.
  6. Chenyang Ge, Nanning Zheng, Dong Wang. Design and Implement of Flat Panel TV Digital Video Post-process Chip. 2008 International Symposium on Artificial Intelligence and Affective Computing (AIAC-08), 2008: 12-19.
  7. Zuoxun Hou, Chenyang Ge, Wenzhe Zhao. “Design and Implementation of High- performance Video Processor for Head-mounted Displays”. IEEE 3DTV Conference, The True Vision - Capture, Transmission and Display of 3D Video (3DTV-CON), 2011.
  8. Longjun Liu, Chenyang Ge. “Spatio-temporal Adaptive 2D to 3D Video Conversion for 3DTV”. IEEE International Conference on Consumer Electronics (ICCE), 2012.
  9. Ruijie Xiao, Chenyang Ge, Bo Liu. “De-interlacing with Motion Compensation and Edge-Dependent Interpolation in Complement Using Judder Pattern”. IEEE International Conference on Consumer Electronics (ICCE), 2005.