研究方向：
射频毫米波集成电路设计
AI驱动模拟射频集成电路设计
代表性论文：
Wang R, Tian Z, Huang J, et al. Automated Design of a 22–41-GHz Phased Array TRX Front-End with Adaptive Analog Temperature Compensation for Multi-Band 5G Communications[C]. 2026 IEEE Custom Integrated Circuits Conference (CICC).
Wang R, Tian Z, Li C, et al. A 24–32-GHz In-Band Full-Duplex T/R Front End With Electrical Balance Duplexer in 65-nm CMOS[J]. IEEE Microwave and Wireless Technology Letters, 2026, 36(4): 629-632.
Wang R, Li C, Qiu K, et al. A Ka -Band Broadband Power Amplifier With Transformer-Based Lossy Magnetically Coupled Resonator Network: Analysis and Design[J]. IEEE Transactions on Microwave Theory and Techniques, 2024, 72(12): 6857-6870.
Wang R, Li C, Wang Y. A Broadband Variable-Gain Low-Noise Amplifier With Low NF and Dual Phase Compensation[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(9): 4086-4090.
Wang R, Zhu W, Wang Y. An Adaptive Analog Temperature Compensated W-Band Front-End With ±0.0033 dB/°C Gain Variation Across −30 °C to 120 °C[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(2): 542-546.
Wang R, Li C, Wang Y. An Improved Through-Only De-Embedding Method for 110-GHz On-Wafer RF Device Characterization[J]. IEEE Microwave and Wireless Components Letters, 2022, 32(10): 1219-1222.
Wang R, Li C, Zhang J, et al. A 18–44 GHz Low Noise Amplifier With Input Matching and Bandwidth Extension Techniques[J]. IEEE Microwave and Wireless Components Letters, 2022, 32(9): 1083-1086.
Wang R, Wang Z, Yin S, et al. A Fully Integrated X-Band Phased-Array Transceiver in 0.13-μm CMOS Technology[C]//2021 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). Hualien, Taiwan: IEEE, 2021: 1-3.
Yin S, Wang R, Zhang J, et al. Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024, 43(3): 705-715.
Yin S, Wang R, Zhang J, et al. Fast Surrogate-Assisted Constrained Multiobjective Optimization for Analog Circuit Sizing via Self-Adaptive Incremental Learning[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42(7): 2080-2093.
Yin S, Wang R, Zhang J, et al. Asynchronous Parallel Expected Improvement Matrix-Based Constrained Multi-Objective Optimization for Analog Circuit Sizing[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(9): 3869-3873.
Zhu W, Wang R, Zhang J, et al. An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS Technology[C]//2022 IEEE Symposium on VLSI Technology and Circuits (VLSI). Honolulu, HI, USA: IEEE, 2022: 102-103.
Zhu W, Wang J, Wang R, et al. A 1V 32.1 dBm 92-to-102GHz Power Amplifier with a Scalable 128-to-1 Power Combiner Achieving 15% Peak PAE in a 65nm Bulk CMOS Process[C]//2022 IEEE International Solid- State Circuits Conference (ISSCC). San Francisco, CA, USA: IEEE, 2022: 318-320.
Zhu W, Wang J, Wang R, et al. 14.5 A 1V W-Band Bidirectional Transceiver Front-End with <1dB T/R Switch Loss, <1°/dB Phase/Gain Resolution and 12.3% TX PAE at 15.1dBm Output Power in 65nm CMOS Technology[C]//2021 IEEE International Solid- State Circuits Conference (ISSCC). San Francisco, CA, USA: IEEE, 2021: 226-228.