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论文期刊

论文标题    A low cost test pattern generator for test-per-clock BIST scheme
作者    Lei, Shaochong; Wang, Zhen; Liu, Zeye; Liang, Feng*
发表/完成日期    2010-10-01
期刊名称    IEICE ELECTRONICS EXPRESS
期卷    7,10
相关文章   
论文简介    Test power and test overhead are crucial to VLSI and SOC testing. This paper proposes a low cost test pattern generator (TPG) for test-per-clock built-in self-test (BIST) scheme. The proposed method utilizes a two-dimensional TPG and a bit-XOR array to reduce area overhead, and generates single input change (SIC) sequences to reduce input transitions of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can achieve high fault coverage and effectively reduce test power.
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