| 论文标题 |
A Low Power Test Pattern Generator for BIST |
| 作者 |
Lei, Shaochong; Liang, Feng*; Liu, Zeye;Wang, Xiaoying |
| 发表/完成日期 |
2010-05-01 |
| 期刊名称 |
IEICE TRANSACTIONS ON ELECTRONICS |
| 期卷 |
5, E93C |
| 相关文章 |
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| 论文简介 |
To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With the proposed reconfigurable LFSR, the reconfigurable Johnson counter, the decompressor and the XOR gate network, the introduced TPG can produce the single input change (SIC) sequences with few repeated vectors. The proposed SIC sequences minimize switching activities of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can effectively save test power, and does not impose high impact on test length and hardware for the scan based design. |
(创新港)
