课题组近期完成的基于数据多路叠加技术的CMOS压摆率控制驱动器芯片研究成果在线发表在IET电路器件与系统，IET Circuits, Devices and Systems上。该工作是课题组在前期2018美国中西部电路与系统会议(MWSCAS)工作的基础上，对压摆率控制理论做了进一步完善，对多路叠加技术的数据和时钟电路设计进行不断优化，并通过0.18um工艺进行设计、流片和测试进行了验证。与前人相比，该工作第一次实现了在几百Mbps的数据率下小于1V/ns的压摆率。该工作主要由课题组博士研究生唐人杰和硕士研究生李凯参与完成。

原文链接：

https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/cds2.12133

Abstract -- A dual‐path open‐loop slew‐rate (SR) controlled CMOS driver is presented in this study. The proposed output driver incorporates a delay‐locked loop (DLL) to minimise the SR variations over process, voltage and temperature, generating delayed versions of transmitted signal by sampling the input data with adjacent phases of the clock from the DLL. A dual‐path open‐loop signal‐superposition technique is introduced to suppress the high‐frequency components of the output driver and thus improves the SR of the CMOS driver. The proposed CMOS output driver achieves a maximum SR of 1.00 and <0.35 V/ns variation operating at 500 Mbps over 32 corners. Both the conventional CMOS driver and the proposed SR controlled output driver were fabricated in a 0.18 μm CMOS process. The proposed driver occupies a compact area of 0.088 mm2 and consumes 55.27 mW with a 1.8 V supply voltage. Measurement results show that the SR of the proposed output driver is <0.816 V/ns, corresponding to 62% reduction compared with that of a conventional output driver, and the total jitter is <0.16 unit interval.