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华为海思与课题组合作项目完成的连续时间线性均衡器芯片发表在IEEE Microwave and Wireless Technology Letters
发布者: 桂小琰 | 2022-12-31 | 6750
Dear Prof. Gui:

It is a pleasure to accept your manuscript entitled "A Continuous-Time Linear Equalizer with Ultra-Fine Gain Adjustment Achieving 0.3-dB DC-Gain Step and 0.9-dB Peaking-Gain Step" in its current form for publication in the IEEE Microwave and Wireless Technology Letters.  The comments of the reviewer(s) who reviewed your manuscript are included at the foot of this letter.

课题组和华为海思高速模拟部高校合作项目资助完成的具有超细颗粒度增益调节的连续时间线性均衡器芯片设计的研究成果发表在IEEE微波理论与技术领域顶刊IEEE MWTL(原IEEE MWCL)上。该工作是课题组在华为海思高速模拟部高校合作项目资助下完成的面向工业界需求的创新工作。芯片展示了一种多级CTLE架构实现超细颗粒度的增益调节,提出了新的增益级电路拓扑结构和设计技术,从而实现直流增益0.3dB和尖峰增益0.9dB的步进,设计带宽超过16GHz。该芯片实现了32Gbps NRZ和64Gbps PAM4数据的无误码传输。该工作主要由课题组博士研究生唐人杰完成。

 

Abstract—A four-stage continuous-time linear equalizer (CTLE) in a 28-nm CMOS process is presented. The proposed CTLE including the output buffer provides peaking gain at Nyquist frequency of ~16 GHz, as well as mid-frequency boosting for low-frequency channel-loss compensation. An ultra-fine gain-tuning scheme employing an extra positive-feedback path is proposed and analyzed, which enables both a large gain-tuning range and fine gain-tuning steps. The dc gain covers a wide range from -3.81 dB to 11.29 dB with a step size of less than 0.3 dB, and the peaking gain at Nyquist frequency can be adjusted from -3.52 dB to 13.48 dB with a step size of less than 0.9 dB, while providing a large boost range of 13 dB. The CTLE consumes 32-mW power from a 0.9-V supply.