A Dual-Path Open-Loop CMOS Slew-Rate Controlled Output Driver with Low PVT Variation

 Abstract—A dual-path open-loop slew-rate controlled CMOS driver is presented. The proposed output driver incorporates a delay-locked loop (DLL) to minimize the slew-rate variation over process, voltage and temperature (PVT). A dual-path open-loop structure is introduced to cancel the high-frequency components of the output signal. Simulation using the Global Foundry 0.18um CMOS process shows that the driver achieves less than 0.6V/ns slew-rate variation operating at 500 Mbps over 16 corners, corresponding to 26% reduction compared with that of a conventional output driver.

Design of A Low-Supply Sensitivity LC VCO with Complementary Varactors

Abstract—Analysis of the effect of supply-induced frequency variation on the LC VCO is described. According to the results of the analysis, the first-order impact on the supply sensitivity is that the varactor’s effective capacitance varies with the supply voltage.  A  novel  compensation  technique  based  on complementary varactors to reduce the supply sensitivity of the LC VCO is proposed with no extra power dissipation, nor phase noise  degradation.  Simulation  results  show  that  this compensation technique reduces the periodic jitter by more than 93%.