搜索
1. 发表论文
期刊论文：
[1] Y. Zhang, X. Yang, H. Liao, Y. Wang, G. Zhang and L. Geng, “A 5-GHz Fractional-N Reference-Sampling PLL With Voltage-Averaging Fractional Phase Detector Achieving an Integer-N-Level Phase Noise,” IEEE Microwave and Wireless Technology Letters. (Early Access)
[2] K. Chang, Q. Xing, G. Jia, Y. Pu, Y. Wang, Y. Wang, Y. Zhang, and G. Zhang, “An Improved DEM for Multibit DT ΣΔMs Based on Poles Splitting Technique and Segmented VQ,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 1, pp. 200–204, 2024.
[3] C. Fan, Y. Zhao, Y. Zhang, J. Yin, L. Geng, and P.-I. Mak, “A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO With a 200-kHz 1/f³ Phase Noise Corner,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 3, pp. 865–869, Mar. 2023.
[4] X. Zhou, X. Gui, M. Gusev, N. Ackovska, Y. Zhang, and L. Geng, “A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, pp. 359–363, Feb. 2022.
[5] X. Gui, R. Tang, Y. Zhang, D. Li, and L. Geng, “A Voltage-Controlled Ring Oscillator With VCO-Gain Variation Compensation,” IEEE Microwave and Wireless Components Letters, vol. 30, no. 3, pp. 288–291, Mar. 2020.
[6] Y. Zhang, A. Sanyal, X. Yu, X. Quang, K. Wen, X. Tang, G. Jin, L. Geng, and N. Sun, “A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction,” IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 602–614, Mar. 2020. (CICC invited submission)
[7] A. Sanyal, X. Yu, Y. Zhang, and N. Sun, “Fractional-N PLL with multi-element fractional divider for noise reduction,” Electronics Letters, vol. 52, no. 10, pp. 809–810, May 2016.
[8] X. Quan, Y. Zhuang, Z. Li, Y. Zhang, and K. Jing. “A 2–22GHz low-imbalanced active balun in 0.18μm SiGe BiCMOS technology”. AEU-International Journal of Electronics and Communications, vol. 70, no. 10, pp. 1367–1373, Oct. 2016.
[9] X. Quan, Y. Zhuang, Z. Li, Y. Zhang, K. Jing, and J. Zhan. “Current generator for 6-bit active phase shifter”. Electronics Letters, vol. 51, no. 15, pp. 1175–1177, Jul. 2015.
[10] Y. Zhang, Y. Zhuang, Z. Li, H. Li, X. Quan, B. Wang, and X. Ren. “A CMOS semi-distributed step attenuator with low insertion loss and low phase distortion”. IEICE Electronics Express, vol. 11, no. 12, pp. 1–5, Jun. 2014.
[11] K. Jing, Y. Zhuang, Z. Li, Y. Du, and Y. Zhang. A SiGe HBT low noise amplifier using on-chip notch filter for K band wireless communication, Microelectronics Journal, vol. 45 no. 6, pp. 683–689, Jun. 2014.
[12] Y. Zhang, Y. Zhuang, Z. Li, X. Quan, and X. Ren. “A broadband 5-bit CMOS step attenuator in small area with low insertion loss”. IEICE Electronics Express, vol. 11, no. 9, pp. 1–5, May 2014.
[13] Y. Zhang, Y. Zhuang, Z. Li, X. Ren, B. Wang, K. Jing, and Z. Qi. “A 5-bit lumped 0.18-μm CMOS step attenuator with low insertion loss and low phase distortion in 3–22 GHz applications”. Microelectronics Journal, vol. 45, no. 4, pp. 468–476, Apr. 2014.
会议论文：
[1] Z. Chen, M. Zhu, H. Li, and Y. Zhang, “A 250-kHz-BW 15.8-ENOB 2nd-Order Noise-Shaping SAR ADC With Multi-Path-Input Floating Inverter Amplifier,” in 2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2023, pp. 184–185.
[2] C. Fa, Y. Zhao, Y. Zhang, J. Y, P.-I Mak, G. Zhang, and L. Geng, “A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS,” in 2023 IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023, pp. 1–2.
[3] M. Gusev, N. Ackovska, V. Zdraveski, E. Stankov, M. Jovanov, M. Dinev, D. Spasov, X. Gui, Y. Zhang, L. Geng, and X. Zhou, “Review of Drowsiness Detection Machine-Learning Methods Applicable for Non-Invasive Brain-Computer Interfaces,” in 2021 29th Telecommunications Forum (℡FOR), 2021, pp. 1–4.
[4] S. Liang, Y. Xin, C. Liang, B. Zhang, Y. Zhang, X. Wang, and L. Geng, “A 0.025% DC Current Mismatch Charge Pump for PLL Applications,” in 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2021, pp. 700–703.
[5] L. Liu, Y. Zhang, L. Dong, Y. Xin, S. Gao, and L. Geng, “A Power Efficient ECG Front-End with Input-Adaptive Gain Reaching 67.6-dB Dynamic Range,” in 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2020, pp. 1–4.
[6] Yanlong Zhang, Arindam Sanyal, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, and Nan Sun, “A 2.4-GHz ΔΣ fractional-N synthesizer with space-time averaging for noise reduction,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Apr. 2019, pp. 1–4.
2. 出版著作
[1] 贾新章, 游海龙, 高海霞, 张岩龙. 电子线路CAD 与优化设计——基于Cadence/PSpice, 北京: 电子工业出版社, 2014.
3. 邀请报告
[1] 2021.11, "Space-Time Averaging: An Approach for Quantization Noise Reduction in Fractional-N PLL", 海思RFIC 高校技术论坛.
[2] 2020.12, "Noise Reduction for Fractional-N Phase-Locked Loops", IEEE 2nd International Conference on Circuits and Systems（IEEE ICCS 2020）.
[3] 2020.06, "A Fractional-N PLL With Space–Time Averaging for Quantization Noise Reduction", 第二届华人芯片设计技术研讨会（ICAC 2020）.
