梁峰
- 教授
- 博士生导师
- 硕士生导师
- 性别：男
- 学历：博士研究生毕业
- 学位：博士
- 所在单位：微电子学院
- 电子邮箱：
- 办公地点：
- 联系方式：
- 学科：电子科学与技术
- 学科：电子科学与技术
A low cost test pattern generator for test-per-clock BIST scheme
- 发布时间：2025-04-30
- 论文名称：A low cost test pattern generator for test-per-clock BIST scheme
- 发表刊物：IEICE ELECTRONICS EXPRESS
- 摘要：Test power and test overhead are crucial to VLSI and SOC testing. This paper proposes a low cost test pattern generator (TPG) for test-per-clock built-in self-test (BIST) scheme. The proposed method utilizes a two-dimensional TPG and a bit-XOR array to reduce area overhead, and generates single input change (SIC) sequences to reduce input transitions of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can achieve high fault coverage and effectively reduce test power.
- 合写作者：Lei, Shaochong; Wang, Zhen; Liu, Zeye; Liang, Feng*
- 卷号：7,10
- 页面范围：672-677
- 是否译文：否
- 发表时间：2010-10-01
- 合写作者：Lei, Shaochong; Wang, Zhen; Liu, Zeye; Liang, Feng*