A Low Power Test Pattern Generator for BIST
- 发布时间:2025-04-30
- 论文名称:A Low Power Test Pattern Generator for BIST
- 发表刊物:IEICE TRANSACTIONS ON ELECTRONICS
- 摘要:To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With the proposed reconfigurable LFSR, the reconfigurable Johnson counter, the decompressor and the XOR gate network, the introduced TPG can produce the single input change (SIC) sequences with few repeated vectors. The proposed SIC sequences minimize switching activities of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can effectively save test power, and does not impose high impact on test length and hardware for the scan based design.
- 合写作者:Lei, Shaochong; Liang, Feng*; Liu, Zeye;Wang, Xiaoying
- 卷号:5, E93C
- 页面范围:696-702
- 是否译文:否
- 发表时间:2010-05-01
- 合写作者:Lei, Shaochong; Liang, Feng*; Liu, Zeye;Wang, Xiaoying